![]() ![]() This macro provides functions like copy(), compare() and print() uvm_field_int: registers a variable in the UVM factory.uvm_object_utils: similar to uvm_component_utils, but the class is derived from the class uvm_object.uvm_component_utils: registers a new class type when the class derives from the class uvm_component.To implement some important methods in classes and variables, UVM provides the UVM Macros. the report_phase can be used to display results from the simulation.the run_phase is the main phase, where the simulation is executed.the connect_phase is used to connect different sub components in a class.the build_phase is responsible for the creation and configuration of the testbench structure constructing the components of the hierarchy.Each element of a UVM testbench is a component derived from an existing UVM class.Įach class has simulation phases that are ordered execution steps implemented as methods. The UVM class library facilitates the implementation of testbenches. The Universal Verification Methodology (UVM) has become the standard for verification of integrated circuits design. ![]()
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